In general, semiconductor materials may be processed in semiconductor technology on or in a substrate (also referred to as a wafer or a carrier), e.g. to fabricate integrated circuits (also referred to as chips). During processing the semiconductor material, certain process steps may be applied, such as forming one or more layers over the substrate, structuring the one or more layers, or contacting the chips. In general, a porous copper layer offers beneficial mechanical properties, for example, in the field of a thick power metallization.
However, a conventional etching mask is limited in its applicability for porous copper layers 100a or also other rough layers 100a, as illustrated in FIG. 1A to FIG. 2C. For structuring, a conventional etching mask is formed 100b from a liquid 12p (e.g. a low viscous photoresist) by spin coating and subsequently patterned 100d by photolithography 100c using exposure to light 110. By applying this procedure to the porous copper layer 100a, the liquid 12p is seeping 108 deep into the porous layer 100a, which complicates processing of the porous copper layer 100a. On the one hand, the deep seeded in liquid 12p is shaded from being exposed to light 110, which, in case of a positive photoresist 116, leads to masking errors and impairs a precise etching of the porous copper layer 100a. On the other hand, the liquid 12p is not fully covering the uneven topography of the porous copper layer 100a. After pattering 100d the etching mask, beside regions 112 in which the porous copper layer 100a is designated to be removed by chemical wet etching 200a, also the protrusions 14p of the porous layer 100a may remain uncovered. During chemical wet etching 200a, the etchant also contacts regions, in which the porous layer is designated to remain undamaged, and etches holes 114 in there (also referred to as pitting). After chemical wet etching 200a, the deep seeded liquid 12p may withstand from being removed out of the porous layer 100a leading to residual photoresist 118.
Therefore, a conventional etching mask lacks in its capability of precise processing and protecting the porous copper layer 100a leading to pitting, as illustrated in FIG. 2C for the usage of a 4.4 micrometer (μm) thick etching mask.
Conventionally, the deposition of the porous layer 100a may lead to a wafer level non-uniformity in the topography of the porous layer 100a. For example, forming the porous copper layer 100a using stencil printing may result in topography differences up to 5 μm between the wafer center and the wafer rim. For example, forming the porous copper 100a layer using plasma-dust may result in a plurality of grooves, which are several micrometers deep. Such topography non-uniformity may accumulate the low viscous photoresist resulting in uncovered regions of the wafer similar to 200a. FIG. 3A illustrates a wafer after preparing a photoresist mask from a liquid by spin coating 300a and photolithography, and FIG. 3B the wafer after etching 300b the wafer. As visible from FIG. 3B, the photoresist mask is removed from the peripheral region during etching since the wafer was substantially uncovered in the peripheral region.
Alternative to a liquid-processed mask, a foil resist may be conventionally used for masking an uneven or porous surface. The foil resist includes a thick foil and an adhesive, which may be structured by photolithography. This approach is cost intensive and effortful.
Alternatively to masking, a porous contact pad may be printed directly according to its designated pattern. This may result in a low pattern accuracy and flat edges of the contact pad.